The present disclosure relates to a Metal Insulator Semiconductor (MIS) type semiconductor device that has a shallow junction depth and a low-resistant diffusion layer, and can be further miniaturized, and a method for fabricating the semiconductor device.
As the scale of integration of semiconductor integrated circuits increases, there is a demand for further miniaturization of a MIS transistor. To achieve this, the MIS transistor needs to have an extension diffusion layer with a shallow junction depth and a low resistance.
Hereinafter, a method for fabricating a conventional MIS transistor will be described with reference to the accompanying drawings.
FIGS. 13A to 13D and 14A to 14D show cross-sectional views of a structure of the conventional MIS transistor in the order in which steps of a fabrication method thereof are performed.
Initially, as shown in FIG. 13A, an N-type impurity (e.g., arsenic (As) ions) is implanted into a semiconductor substrate 1 made of P-type silicon at an implantation energy of about 140 keV and an implantation dose of about 1×1012/cm2. Thereafter, phosphorus (P) ions are implanted into an upper portion of the semiconductor substrate 1 at an implantation energy of about 260 keV and an implantation dose of about 4×1012/cm2 for the first ion implantation and at an implantation energy of about 540 keV and an implantation dose of about 1×1013/cm2 for the second ion implantation. By performing predetermined thermal processing immediately after the ion implantation, an N-type well 2 and an N-type channel diffusion layer 3 are formed in a channel region of the semiconductor substrate 1.
Next, as shown in FIG. 13B, a gate insulating film 4 having a film thickness of about 2.2 nm is formed on the semiconductor substrate 1. A polycrystal silicon film having a film thickness of about 200 nm is formed on the gate insulating film 4. Thereafter, the polycrystal silicon film is subjected to patterning to form a gate electrode 5. In this case, the gate insulating film 4 may have the same pattern as that of the gate electrode 5.
Next, as shown in FIG. 13C, ion implantation of an N-type impurity (e.g., As ions) is performed at an implantation energy of about 130 keV and an implantation dose of about 7×1013/cm2, to form pocket impurity implanted layers 6A.
Next, as shown in FIG. 13D, ion implantation of fluorine is performed at an implantation energy of about 25 keV and an implantation dose of about 5×1014/cm2, to perform so-called preamorphization that allows formation of P-type extension diffusion layers having shallow junction depths.
Next, as shown in FIG. 14A, ion implantation of a P-type impurity (e.g., boron (B) ions) is performed at an implantation energy of about 1.5 keV and an implantation dose of about 5×1014/cm2 using the gate electrode 5 as a mask, to form extension impurity implanted layers 7A.
Next, as shown in FIG. 14B, for example, an insulating film made of silicon nitride having a film thickness of about 50 nm is deposited. The deposited insulating film is then subjected to anisotropic etching having a higher etch rate in a vertical direction, so that sidewalls 8 made of silicon nitride are formed on side surfaces of the gate electrode 5.
Next, as shown in FIG. 14C, ion implantation of a P-type impurity (e.g., boron difluoride (BF2) ions) is performed at an implantation energy of about 30 keV and an implantation dose of about 3×1015/cm2 using the gate electrode 5 and the sidewalls 8 as a mask, to form P-type impurity implanted layers 9A.
Next, as shown in FIG. 14D, the semiconductor substrate 1 is subjected to thermal processing at high temperature and for a short time, to form P-type extension diffusion layers 7 having shallow junction depths from the respective extension impurity implanted layers 7A in an upper portion of the semiconductor substrate 1 below the respective sidewalls 8, and N-type pocket diffusion layers 6 from the respective pocket impurity implanted layers 6A below the respective P-type extension diffusion layers 7. Also, P-type source and drain diffusion layers 9 having deeper junction depths than those of the respective N-type pocket diffusion layers 6 are formed from the respective P-type impurity implanted layers 9A in the semiconductor substrate 1 farther outside than the respective sidewalls 8.
As described above, in the conventional MIS semiconductor device fabricating method, as shown in FIG. 14A, the implantation energy of boron ions used for extension implantation to form the P-type extension diffusion layer 7 is reduced so that the P-type extension diffusion layer 7 has a shallow junction.